The present invention relates generally to current sources and more specifically to high impedance differential to single-ended current converters.
Ideal current sources have output impedance of infinity and provide a specific current level. In actuality, these characteristics can only be approximated. In all implementations of current sources, they deviate from the ideal in at least two ways. The first is a parasitic parallel resistance which lowers the current source impedance from its ideal value of infinity. A second deviation is in the current level itself from the desired value because of current errors and biasing errors. This is particularly bothersome in bipolar current sources. Since the collector impedance of a bipolar transistor is inversely proportional to the current level, it is difficult to design a high impedance current source for high current levels with bipolar transistors. Also, it is difficult to set a precise current level since base current errors accumulate in bipolar transistors and drift as the bipolar transistor parameters drift with temperature changes.
A typical bipolar current source or current stack is illustrated in FIG. 1 including transistors Q1 and Q2 having their emitter-to-collector current paths connected between nodes N3 and N4. Their bases are connected to nodes N1 and N2. Nodes N1, N2 and N4 are DC bias levels with the output current I-OUT being being at node 3 and being represented by equation (1). EQU I.sub.out =ICQ2=IEQ1-IBQ1-IBQ2 (1)
The desired value for an ideal current source is IEQ1. The base currents for transistors Q1 and Q2, namely IBQ1 and IBQ2, represent error terms.
The output impedance is dominated by the collector-base impedance of Q2, which is given by equation (2), EQU R=1/hobQ2 (2)
as the inverse of the small signal grounded base output admittance hobQ2. hob is a linear function of collector current level, so as the magnitude of the current source increases, its impedance decreases and deviates further from the ideal.
The prior art generally includes a sensor which provides a feedback to the input to cancel input bias and noise currents. A typical example in a differential bipolar amplifier is U.S. Pat. No. 4,639,684 to Laude. In operational amplifiers, the output impedance of a voltage gain stage has been increased by feeding back current from the output current stage as shown in U.S. Pat. No. 4,560,948 to Prentice and Cotreau.
Thus, it is an object of the present invention to reduce the current error produced by the base currents of the transistors Q1 and Q2 as well as minimizing the reduction of output impedance due to the collector impedance of the output transistor, and to make these improvements independent of the magnitude of the current source.
Another object of the present invention is to provide a high impedance differential to single-ended current converter or transconductance stage.
These and other objects of the invention are attained by providing a correction circuit connected between the subtracting means for subtracting the output current of a first output terminal of a first variable current source from the current at a second or output terminal of a second variable current source a differential current to single ended current converter. The correction circuit senses the incremented current through output transistors at the second output, which forms the converter output, and provides the sensed incremented current to the output to cancel the effect of the incremented current through the output transistors on the impedance of the converter's output terminal. This cancellation of incremented current maintains the output impedance at substantially infinity without substituting a parallel impedance circuit.
The output circuitry includes a first transistor having its conduction path connected in series between a first reference terminal and the converter output terminal and a second transistor having its conduction path connected between the subtracting circuit and the converter output terminal. The correction circuit is connected to the control terminals of the first and second transistors and the conduction path of the second transistor to monitor the current at the control terminals of the first and second transistor and apply the correcting current to the conduction path of the second transistor.
The correction circuit includes a third transistor having its conduction path connected between the control terminals of the first and second transistor and a fourth transistor having its conduction path connected between the second transistor's control terminal and a portion of the conduction path of the second transistor where it is connected to the subtracting circuit. The first, third and fourth transistors are of the same conductivity type and the second transistor is of a different conductivity type. Wherein the transistors are bipolar transistors, the third and fourth transistors have alpha's of approximately 1. The subtracting circuit includes a current mirror.
A high output impedance current stage may also be formed using the previously described circuitry wherein the first and second transistors form an output stage connecting a first and second current source and a current input. The correction circuit provides appropriate compensation and maintains a high output impedance as previously described.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.